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TMCNet:  U.S. Patents Awarded to Inventors in Oregon (Jan. 3)

[January 03, 2013]

U.S. Patents Awarded to Inventors in Oregon (Jan. 3)

(Targeted News Service Via Acquire Media NewsEdge) Targeted News Service Targeted News Service ALEXANDRIA, Va., Jan. 3 -- The following federal patents were awarded to inventors in Oregon.

*** Mentor Graphics Assigned Patent for Delta Retiming in Logic Simulation ALEXANDRIA, Va., Jan. 3 -- Mentor Graphics, Wilsonville, Ore., has been assigned a patent (8,346,529) developed by Sachin Kakkar, Delhi, India, and John Ries, Wilsonville, Ore., for a "delta retiming in logic simulation." The abstract of the patent published by the U.S. Patent and Trademark Office states: "Aspects of the present invention are directed to improving the speed of event-driven simulation by manipulating delta delays in a system model to reduce delta cycle executions. The manipulation is performed in a manner that preserves delta cycle accurate timing on selected signals of the system, which may be of interest to a designer. Methods and systems are provided for identifying the signals of interest, and for determining portions of the design that may have delta delays retimed. Preserving the timing on the signals of interest ensures that race conditions and glitches present in the design on the signals of interest are still viewable by the designer. To reduce simulation time, delta delays may be moved from high activity signals to low activity signals, the total number of delta delays may be reduced, or a number of processes executed may be reduced." The patent application was filed on Dec. 29, 2009 (12/648,600). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,346,529&OS=8,346,529&RS=8,346,529 Written by Satyaban Rath; edited by Hemanta Panigrahi.


*** Intel Assigned Patent for Method, Apparatus and System for Maintaining Mobility Resistant IP Tunnels Using a Mobile Router ALEXANDRIA, Va., Jan. 3 -- Intel, Santa Clara, Calif., has been assigned a patent (8,345,712) developed by Kapil Sood, Beaverton, Ore., Jesse R. Walker, Portland, Ore., and Tsung-Yuan Tai, Portland, Ore., for a "method, apparatus and system for maintaining mobility resistant IP tunnels using a mobile router." The abstract of the patent published by the U.S. Patent and Trademark Office states: "A method, apparatus and system enable a mobile device to roam while maintaining a persistent IP tunnel. Specifically, a mobile router may be utilized to enable a mobile device to maintain a persistent IP tunnel while the device roams. In one embodiment, the mobile device is a virtual host and the mobile router is a virtual mobile router." The patent application was filed on Dec. 13, 2011 (13/323,890). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=83,45,712.PN.&OS=PN/83,45,712&RS=PN/83,45,712 Written by Amal Ahmed; edited by Jaya Anand.

*** Mentor Graphics Assigned Patent ALEXANDRIA, Va., Jan. 3 -- Mentor Graphics, Wilsonville, Ore., has been assigned a patent (8,347,159) developed by five co-inventors for a "compression based on deterministic vector clustering of incompatible test cubes." The co-inventors are Grzegorz Mrugalski, Swarzedz, Poland, Nilanjan Mukherjee, Wilsonville, Ore., Janusz Rajski, West Linn, Ore., Dariusz Czysz, Wielkopolski, Poland, and Jerzy Tyszer, Poznan, Poland.

The abstract of the patent published by the U.S. Patent and Trademark Office states: "The test data compression scheme is based on deterministic vector clustering. Test cubes that feature many similar specified bits are merged into a parent pattern in the presence of conflicts. The parent pattern along with a control pattern and incremental patterns representing conflicting bits are encoded efficiently. A tri-modal decompressor may be used to decompress the test data." The patent application was filed on March 5, 2010 (12/718,813). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8,347,159.PN.&OS=PN/8,347,159&RS=PN/8,347,159 Written by Kusum Sangma; edited by Anand Kumar.

*** Cisco Technology Assigned Patent for Inspection and Rewriting of Cryptographically Protected Data from Group VPNs ALEXANDRIA, Va., Jan. 3 -- Cisco Technology, San Jose, Calif., has been assigned a patent (8,347,073) developed by four co-inventors for an "inspection and rewriting of cryptographically protected data from group VPNs." The co-inventors are David A. McGrew, Poolesville, Md., Mark Baugher, Portland, Ore., Saul Adler, West Hempstead, N.Y., and William C. Melohn, Mountain View, Calif.

The abstract of the patent published by the U.S. Patent and Trademark Office states: "Systems, methods, and other embodiments associated with processing secure network traffic are described. One example method includes determining whether a device is a preconfigured member of a group key system. If the device is not a preconfigured member then the method selectively establishes membership in the group key system by requesting membership from a group controller. The example method may also include receiving a set of keys from the group controller and being assigned a role by the group controller. The method may further include processing secure network traffic as an inspection point, a rewriting point, and/or a validation point based on the received set of keys and the assigned role(s)." The patent application was filed on Sept. 5, 2008 (12/231,813). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8,347,073.PN.&OS=PN/8,347,073&RS=PN/8,347,073 Written by Kusum Sangma; edited by Anand Kumar.

*** Intel Assigned Patent for Replay Instruction Morphing ALEXANDRIA, Va., Jan. 3 -- Intel, Santa Clara, Calif., has been assigned a patent (8,347,066) developed by four co-inventors for a replay instruction morphing. The co-inventors are Douglas M. Carmean, Beaverton, Ore., David J. Sager, Portland, Ore., Thomas F. Toll, Portland, Ore., and Karol F. Menezes, Portland, Ore.

The abstract of the patent published by the U.S. Patent and Trademark Office states: "Replay instruction morphing. One disclosed apparatus includes an execution unit to execute an instruction. A replay system replays an altered instruction if the execution unit executes the instruction erroneously." The patent application was filed on Feb. 28, 2005 (11/069,004). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8,347,066.PN.&OS=PN/8,347,066&RS=PN/8,347,066 Written by Kusum Sangma; edited by Anand Kumar.

*** Intel Assigned Patent for Link Performance Abstraction for ML Receivers Based on RBIR Metrics ALEXANDRIA, Va., Jan. 3 -- Intel, Santa Clara, Calif., has been assigned a patent (8,347,152) developed by four co-inventors for a "link performance abstraction for ML receivers based on RBIR metrics." The co-inventors are Hongming Zheng, Beijing, Wu May, Shanghai, China, Yang-seok Choi, Portland, Ore., and Senjie Zhang, Beijing.

The abstract of the patent published by the U.S. Patent and Trademark Office states: "A PHY abstraction mapping between the link level and system level performance is presented based on mapping between the mean RBIR (Received Bit Information Rate) of the transmitted symbols and their received LLR values after symbol-level ML detection in SISO/MIMO wireless systems, such as WiMAX. In MIMO antenna configuration, the mapping is presented for both vertical and horizontal encoding. An embodiment of this invention provides the PER/BLER prediction in the actual system, enabling the system to use more aggressive methods to improve the system performance." The patent application was filed on Sept. 10, 2008 (12/207,497). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8,347,152.PN.&OS=PN/8,347,152&RS=PN/8,347,152 Written by Kusum Sangma; edited by Anand Kumar.

*** Intel Assigned Patent for Method and Apparatus to Maintain Data Integrity in Disk Cache Memory During and After Periods of Cache Inaccessibility ALEXANDRIA, Va., Jan. 3 -- Intel, Santa Clara, Calif., has been assigned a patent (8,347,141) developed by four co-inventors for a "method and apparatus to maintain data integrity in disk cache memory during and after periods of cache inaccessibility." The co-inventors are Sanjeev N. Trika, Hillsboro, Ore., Michael K. Eschmann, Lees Summit, Mo., Jeanna N. Matthews, Massena, N.Y., and Vasudevan Srinivasan, Hillsboro, Ore.

The abstract of the patent published by the U.S. Patent and Trademark Office states: "A volatile or nonvolatile cache memory can cache mass storage device read data and write data. The cache memory may become inaccessible, and I/O operations may go directly to the mass storage device, bypassing the cache memory. A log of write operations may be maintained to update the cache memory when it becomes available." The patent application was filed on April 14, 2011 (13/086,636). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8,347,141.PN.&OS=PN/8,347,141&RS=PN/8,347,141 Written by Kusum Sangma; edited by Anand Kumar.

*** Lexcycle Assigned Patent ALEXANDRIA, Va., Jan. 3 -- Lexcycle, Portland, Ore., has been assigned a patent (8,347,232) developed by Marc Prud'Hommeaux, Portland, Ore., and Augustus A. White, Houston, for an interactive user interface.

The abstract of the patent published by the U.S. Patent and Trademark Office states: "Methods and apparatuses are provided for navigating an electronic document. In one implementation, a method includes executing a command associated with a region selected by a tap gesture. In another implementation, a method includes displaying a slider on a slide bar including an expanded part corresponding to a section of the electronic document. The expanded part is disproportionately larger than other parts of the slide bar corresponding to other sections of the electronic document. Methods and apparatuses are provided for activating an element of an electronic document. In one implementation, a method includes activating the element selected by a touch gesture. Methods and apparatuses are provided for controlling a perceived brightness of an electronic document. In one implementation, a method includes displaying a partially opaque graphical object in front of the electronic document. The perceived brightness of the electronic document being based on an opacity of the graphical object." The patent application was filed on July 10, 2009 (12/500,792). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8,347,232.PN.&OS=PN/8,347,232&RS=PN/8,347,232 Written by Kusum Sangma; edited by Anand Kumar.

*** Intel Assigned Patent for Posting Weakly Ordered Transactions ALEXANDRIA, Va., Jan. 3 -- Intel, Santa Clara, Calif., has been assigned a patent (8,347,035) developed by eight co-inventors for posting weakly ordered transactions. The co-inventors are Geeyarpuram N. Santhanakrishnan, Portland, Ore., Julius Mandelblat, Haifa, Israel, Ehud Cohen, Kiryat Motskin, Israel, Larisa Novakovsky, Haifa, Israel, Zeev Offen, Folsom, Calif., Michelle J. Moravan, Haifa, Israel, Shlomo Raikin, Geva Carmel, Israel, and Ron Gabor, Raanana, Israel.

The abstract of the patent published by the U.S. Patent and Trademark Office states: "A processor may comprise a core area, a control unit, an uncore area. The core area may comprise multiple processing cores and line-fill buffers. A first processing core of the core area may store a first weakly ordered transaction in a first line-fill buffer. The firs processing core may offload the first weakly ordered transaction to the extended buffer space provisioned in the uncore area after receiving a request from the uncore area. The first processing core may then de-allocate the first line-fill buffer after the first weakly ordered transaction is offloaded to the extended buffer space. The uncore may then post the first weakly ordered transaction to a memory or a memory system. The control unit may track the first weakly ordered transaction to ensure that the first weakly ordered transaction is posted to the memory or the system." The patent application was filed on Dec. 18, 2008 (12/338,919). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8,347,035.PN.&OS=PN/8,347,035&RS=PN/8,347,035 Written by Kusum Sangma; edited by Anand Kumar.

*** Intel Assigned Patent for Systems and Methods for Fast State Modification of at Least A Portion of Non-volatile Memory ALEXANDRIA, Va., Jan. 3 -- Intel, Santa Clara, Calif., has been assigned a patent (8,347,029) developed by four co-inventors for "systems and methods for fast state modification of at least a portion of non-volatile memory." The co-inventors are Sanjeev N. Trika, Hillsboro, Ore., Debra Hensgen, Portland, Ore., Han H. Chau, Portland, Ore., and Michael Johnston, Tigard, Ore.

The abstract of the patent published by the U.S. Patent and Trademark Office states: "A method is provided for reducing the number of writes in a non-volatile memory (122). The method involves writing data in the non-volatile memory and determining a set of data from the data in the non-volatile memory to be written to a removable memory (126) that is operatively coupled to the non-volatile memory (e.g., a NAND memory). The method also involves writing the set of data to the removable memory (e.g., a hard disk) from the non-volatile memory. The method further involves writing a delineation marker (e.g., a sequence number) to the non-volatile memory specifying that the set of data has been written to the removable memory. Notably, the metadata of the data in the non-volatile memory comprises at least one marker set as a specific marker type (e.g., a valid marker and a dirty marker)." The patent application was filed on Dec. 28, 2007 (11/966,826). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8,347,029.PN.&OS=PN/8,347,029&RS=PN/8,347,029 Written by Kusum Sangma; edited by Anand Kumar.

*** Intel Assigned Patent for Automatic Dynamic Processor Operating Voltage Control ALEXANDRIA, Va., Jan. 3 -- Intel, Santa Clara, Calif., has been assigned a patent (8,347,127) developed by Paul Zagacki, Lake Oswego, Ore., for an "automatic dynamic processor operating voltage control." The abstract of the patent published by the U.S. Patent and Trademark Office states: "A technique to adjust a processor's operating voltage dynamically while preventing a user from placing the processor into a harmful operating voltage state in relation to the core/bus frequency ratio of the processor. More particularly, embodiments of the invention relate to a technique to control the operating voltage of the processor as a function of the processor's bus and/or core clock frequency." The patent application was filed on Feb. 10, 2011 (13/024,592). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8,347,127.PN.&OS=PN/8,347,127&RS=PN/8,347,127 Written by Kusum Sangma; edited by Anand Kumar.

*** Intel Assigned Patent for Method and System for Device Address Translation for Virtualization ALEXANDRIA, Va., Jan. 3 -- Intel, Santa Clara, Calif., has been assigned a patent (8,347,063) developed by Kiran Panesar, Hillsboro, Ore., and Philip Lantz, Cornelius, Ore., for a "method and system for device address translation for virtualization." The abstract of the patent published by the U.S. Patent and Trademark Office states: "A method of improving USB device virtualization is proposed that allows giving virtual machines (VMs) direct access to USB devices with a combination hardware and software solutions. The USB host controller replaces device identifiers assigned by the VM with real device identifiers that are unique in the system. The real device identifiers are assigned by the virtual machine monitor (VMM) or the host controller." The patent application was filed on Aug. 19, 2005 (11/207,545). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8,347,063.PN.&OS=PN/8,347,063&RS=PN/8,347,063 Written by Kusum Sangma; edited by Anand Kumar.

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